(a) Field of the Invention
The present invention relates to a semiconductor device and, more particularly, to an insulated gate field effect transistor (IGFET) such as MOSFET.
(b) Description of the Related Art
Fabrication of a small sized and high density semiconductor device is now aggressively in progress, and highly integrated devices such as memory or logic devices with a design rule of 0.15 .mu.m.about.0.25 .mu.m are being developed. As a result of very large scale integration of semiconductor devices, the dimensional reduction of the width of the gate electrode or diffused region and the reduction of the film thickness of semiconductor device have become more important.
Such semiconductor devices are fabricated by using a complementary MOS transistor (CMOS) as a base component. As a result, wells are provided on the surface area of the semiconductor substrate. For example, p-channel MOS transistor is fabricated in an n-well (region) and an n-channel MOS transistor is fabricated on a p-well (region).
For a higher integration of the semiconductor device, the reduction of a distance between a diffused region for a source or drain and a diffused region for a well is also important.
A conventional technique is described hereafter for the arrangement of the source/drain diffused region and a diffused region for the well.
FIG. 1A is a circuit diagram of a CMOS inverter, shown for an exemplary purpose, FIG. 1 is a top plan view of the CMOS inverter of FIG. 1A, and FIG. 2 is a cross-sectional view taken along line A-A' in FIG. 1B.
In FIG. 1A, the gate of a p-channel MOS transistor Q1 and the gate of an n-channel MOS transistor Q2 are connected together to an input IN. The drains of transistors Q1 and Q2 are also connected together to an output OUT. The source of the p-channel MOS transistor Q1 is connected to a power source line Vdd and the source of the n-channel MOS transistor Q2 is connected to the ground line Vss.
In FIGS. 1B and 2, an n-well 102 is formed on a silicon substrate 101, and a p-type diffused region 103 for the source and a p-type diffused region 104 for the drain of the p-channel NOS transistor Q1 are formed within the n-well 102. A diffused region 105 for the n-well contact is formed in the n-well 102. The p-type source region 103 and the n-well contact region 105 are connected together to Vdd line 106 through the openings provided therefor.
Similarly, an n-type drain region 107, an n-type source region 108 and a substrate contact region 109 are disposed on the surface area of the silicon substrate 101. The n-type diffused region 108 and the substrate contact region 109 are connected together to Vss line 110 through the openings provided therefor.
A common gate electrode 111 is formed for both the p-channel MOS transistor Q1 and the n-channel MOS transistor Q2 and connected to the input IN. Both the p-type drain region 104 of the p-channel MOS transistor Q1 and the n-type drain region 107 of the n-channel MOS transistor Q2 are connected together to the output line 112 through the openings provided therefor. The n-well 102 has a depth of about 4 .mu.m.about.8 .mu.m, for example. The p-type source region 103 of the p-channel MOS transistor Q1, the p-type drain region 104 thereof and the well contact region 105 are disposed within the n-well region 102. Here, these diffused regions contain a heavy density of boron as an impurity element. Also, the n-type drain region 107 of the n-channel MOS transistor Q2, the n-type source region 108 and the substrate contact region 109 are formed on the surface area of the silicon substrate 101. Field oxide films 113 and 113a are selectively provided on the surface area for the separation of the transistors.
A gate oxide film 114 and a gate electrode 115 are formed for the p-channel MOS transistor Q1. Similarly, a gate oxide film 116 and a gate electrode 117 are formed for the n-channel MOS transistor Q2. Both the gate electrodes 115 and 117 are connected together to the input IN.
An interlayer dielectric film 118 is formed on the gate electrodes 115 and 117, Vdd line 106 is formed for connecting together the p-type source region 103 and the well-contact region 105. Similarly, the Vss line 110 is formed for connecting together the n-type source region 108 and the substrate-contact region 109. Both the p-type drain region 104 and the n-type drain region 107 are connected together to the output line 112.
In the conventional semiconductor device as described above, it is generally known that a small isolation distance between diffused regions involves a parasitic bipolar transistor formed in the CMOS structure which sometime causes a latch-up failure. Moreover, the small isolation distance involves a low withstand voltage due to punch-through between the source/drain region of the MOS transistor formed within the well and the silicon substrate.
Patent Publication No.JP-A-58(1983)-201358 shows a solution for the problem latch-up by forming a heavily doped n-type diffused region on the bottom part of an n-well.
Patent Publication No.JP-A-61(1986)-7033 shows a solution for the problem punch-through and the resultant lowering of the with stand voltage by making a distance between heavily diffused regions of the same conductivity type within a well larger than the distance between other regions.
In order for fabrication of a highly integrated CMOS semiconductor, a distance X.sub.1 between the n-well 102 and the n-type drain region 108, and a distance Y.sub.1 between the n-well 102 and the n-type source region 107 shown in FIGS. 1B and 2 should be reduced as much as possible.
In the conventional technique, the lower limit of X.sub.1 or Y.sub.1 is determined based on the withstand voltage between the n-well 102 and the n-type diffused region 107 or 108, as a result of which X.sub.1 and Y.sub.1 are determined as an equal value.
In the conventional device as discussed above, the absolute threshold voltage (Vt) of a MOS transistor is slightly lowered in a region adjacent to the well on the silicon substrate, if the lower limit is actually applied to the CMOS transistor. Specifically, a positive threshold voltage of an n-channel MOS transistor disposed most adjacent to an n-well is about 40 mV lowered from a normal threshold voltage, for example, 0.8 volt. Similarly, a negative threshold voltage of a p-channel MOS transistor disposed most adjacent to the p-well is about 50 mV raised from a normal threshold voltage, for example, -1.0 volt. Such a phenomenon of the threshold voltage fluctuation was confirmed by the inventor.
Such a small threshold voltage fluctuation is not critical for semiconductor devices of current technique. However, the small fluctuation will cause a significant problem when the gate width of a MOS transistor is made smaller due to the miniaturization of semiconductor devices, or the operating voltage for the MOS transistor is lowered in the semiconductor devices. Particularly, it will cause a critical problem in an integrated-circuit such as DRAM comprising a sense amplifier for amplifying a fine voltage.